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Intel(R)
82575 Gigabit Ethernet Controller
Datasheet v1.00
June 2007 317697-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL(R) PRE-RELEASE PRODUCTS. Please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any Intel(R) pre-release product, including any evaluation, development or reference hardware and/or software product (collectively, "Pre-Release Product"). By using the Pre-Release Product, you indicate your acceptance of these terms, which constitute the agreement (the "Agreement") between you and Intel Corporation ("Intel"). In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. The 82575 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel(R) Pentium(R) 4 processor supporting HT Technology and a HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/ products/ht/Hyperthreading_more.htm for additional information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005-2007, Intel Corporation. All Rights Reserved.
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82575 Gigabit Ethernet Controller Datasheet
Contents
1.0 Introduction .............................................................................................................. 1 1.1 Document Scope ................................................................................................. 1 1.2 Reference Documents .......................................................................................... 1 1.3 Block Diagram .................................................................................................... 3 Features of the 82575 Gigabit Ethernet Controller ..................................................... 5 2.1 PCI Express Features ........................................................................................... 5 2.2 MAC-Specific Features ......................................................................................... 5 2.3 PHY-Specific Features .......................................................................................... 6 2.4 Host Offloading Features ...................................................................................... 7 2.5 Manageability Features ........................................................................................ 7 2.6 Additional Device Features.................................................................................... 8 2.7 Technology Features............................................................................................ 9 Signal Descriptions and Pinout List.......................................................................... 10 3.1 Signal Type Definitions....................................................................................... 10 3.2 PCI Express Interface ........................................................................................ 10 3.3 Power Management Signals ................................................................................ 11 3.4 System Management Interface Signals ................................................................. 12 3.5 MDIO Signals.................................................................................................... 12 3.6 SPI EEPROM and FLASH Signals .......................................................................... 13 3.7 LED Signals ...................................................................................................... 13 3.8 Other Signals.................................................................................................... 14 3.9 Crystal Signals .................................................................................................. 14 3.10 PHY Analog Signals............................................................................................ 15 3.11 Serializer/Deserializer Signals ............................................................................. 16 3.12 Test Interface Signals ........................................................................................ 16 3.13 Power Supply Connections.................................................................................. 17 3.13.1 Digital and Analog Supplies ..................................................................... 17 3.13.2 Grounds, Reserved Pins and No Connects .................................................. 17 Pinout/Signal Name ................................................................................................ 17 Power Requirements ............................................................................................... 38 5.1 Targeted Absolute Maximum Ratings.................................................................... 38 5.2 Targeted Recommended Operating Conditions....................................................... 38 Thermal ................................................................................................................... 42 Electrical Specification............................................................................................. 42 7.1 DC Specifications .............................................................................................. 42 7.2 Resets ............................................................................................................. 46 7.3 Pull-up and Pull-down Specifications and Signals ................................................... 46 7.4 Targeted AC Characteristics ................................................................................ 49 Crystal Requirements .............................................................................................. 55 LED Configuration.................................................................................................... 55
2.0
3.0
4.0 5.0
6.0 7.0
8.0 9.0
10.0 Mechanical Information ........................................................................................... 56 10.1 Targeted Package Information ............................................................................ 56 10.2 Visual Pin Assignments ...................................................................................... 59
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82575 Gigabit Ethernet Controller Datasheet
Revision History
Date August 2005 January 2006 July 2006 February 2007 June 2007
Revision 0.10 0.25 0.50 0.75 1.0
Description Initial Release Added general information, updated pins list Removed information regarding Fast Management Link; added general information Added measured power values; corrected Visual Pin Assignment Diagrams (RBIAS0_N and RBIAS1_N corrected to VSS). Updated classification, changed RMII to NC-SI, updated pin list, updated NC-SI timing specs. changed LAN_PWR_GOOD to Internal_Power_On_Reset.
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82575 Gigabit Ethernet Controller Datasheet
1.0
Introduction
The Intel(R) 82575 Gigabit Ethernet Controller is a single, compact component with two fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The device uses the PCI Express Base Specification, Rev.1.1RD. The Intel 82575 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode to connect to external PHY, either on-board or via the SFP connector. The Intel 82575's on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. Enhanced pass-through capabilities also allow system remote control over standardized interfaces. Also included is a new manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An internal management interface called MDIO enables the MAC (and software) to monitor and control the PHY. Both ports support the Wake on LAN feature. The 82575 Gigabit Ethernet Controller with PCI Express architecture is designed for high performance and low memory latency. The device is optimized to connect to a system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the 82575 controller can connect to an I/O Control Hub that has a PCI Express interface. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the 82575 controller efficiently handles packets with minimum latency. The 82575 controller includes advanced interrupt handling features, including MSI-X support. The 82575 uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82575 operation can be configured using EEPROM and FLASH; it can be also be used in EEPROM-less configurations. The 82575 is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).
1.1
Document Scope
This document contains targeted datasheet specifications for the 82575 Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: 82575 Gigabit Ethernet Controller Design Guide. Intel Corporation. Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation. PCI Express Base Specification, Revision 1.1.
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82575 Gigabit Ethernet Controller Datasheet
PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group. PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group. IEEE Standard 802.3, 2002 Edition. Institute of Electrical and Electronics Engineers (IEEE). This version incorporates various IEEE standards previously published separately. System Management Bus (SMBus) Specification, SBS Implementers Forum, Ver. 2.0, August 2000. INF-8074i Specification for SFP (Small Form factor Pluggable) Transceiver.
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82575 Gigabit Ethernet Controller Datasheet
1.3
Block Diagram
EEPROM
FLASH
Host
PCI Express (x4)
LAN Port 0 SerDes/SGMII/SFP
82575
RMII Management SMB SerDes/SGMII/SFP LAN Port 1
LEDs
SDP
JTAG
Figure 1.
82575 Gigabit Ethernet Controller Block Diagram
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82575 Gigabit Ethernet Controller Datasheet
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82575 Gigabit Ethernet Controller Datasheet
2.0
2.1
Features of the 82575 Gigabit Ethernet Controller
PCI Express Features
Features * * *
Benefits Bus sharing not required Low latency path to memory Relieves congestion for IO devices connected to ICH Supports Gigabit Ethernet at full wire speed Compatible extensions to PCI power management and ACPI PE_WAKE_N available for wakeup event Less congested board routing
Uses x4 PCI Express interface on MCH device Peak bandwidth 2 GB/s in each direction per PCI Express lane PCI Express Power Management High bandwidth density per pin 64-bit address support for systems using more than 4 GB of physical memory
* * * * *
2.2
MAC-Specific Features
Features
Benefits * * * * * * * * * * * * * Accelerated TCP I/O. Network packets handled without waiting or buffer overflow. Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Efficient use of PCI Express bandwidth Efficient packet prioritization Efficient use of PCI Express bandwidth Low latency data handling Superior DMA transfer rate performance No external FIFO memory requirements FIFO size adjustable to application Simple software programming model Efficient system memory and use of PCI Express bandwidth
I/O Acceleration Technology2 (IOAT2) Four optimized transmit and receive queues IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Caches up to 64 packet descriptors (per queue) Separate transmit and receive queues per port Programmable host memory receive buffers (256 Bytes to 16 KBytes) and cache line size (64 Bytes to 128 Bytes) Wide, pipelined internal data path architecture Dual 8 KByte configurable Transmit and Receive FIFO buffers Descriptor ring management hardware for transmit and receive Optimized descriptor fetching and write-back mechanisms
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82575 Gigabit Ethernet Controller Datasheet
Features
Benefits * * * Maximizes system performance and throughput Enables jumbo frames Part of the PCI standard, enables sending interrupt messages to specific CPUs in a multiplecores platform
Mechanism available for reducing interrupts generated by transmit and receive operations Support for transmission and reception of packets up to 9.5 kB MSI-X Support
2.3
PHY-Specific Features
Features
Benefits
IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Line Length >140m Operates with worst-case cable Supports carrier extension and packet bursting (half duplex) Auto-negotiation with support for Next Page PMA loopback capable (No echo cancel) Advanced Power Management * * Low power link up "Smart Power Down - Link disconnect
Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Reliable operation at greater distances Reliability Improves performance Improves performance and reliability Facillitates testing/troubleshooting Improves power capabilities Improves performance Ease of design
Support for limited auto MDIO register init limited number of registers Fiber/Copper switch support SERDES Signal Detect and support of non-AN partner Smart Speed Auto crossover for MDI Smart Power Down Advanced Cable Diagnostics
2.4
Host Offloading Features
Features
Benefits * * * * Lower CPU utilization Increased throughput and lower CPU utilization Large send offload feature (in Microsoft* Windows* XP) compatible Checksum and segmentation capability extended to new standard packet type
Transmit and receive IP, TCP and UDP checksum off-loading capabilities Transmit TCP segmentation IPv6 Offloading
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82575 Gigabit Ethernet Controller Datasheet
Features
Benefits * * * * * Helps the driver to focus on the relevant part of the packet without the need to parse it. 16 exact matched packets (unicast or multicast) 4096-bit hash filter for multicast frames Promiscuous (unicast and multicast) transfer mode support Optional filtering of invalid frames Ability to create multiple virtual LAN segments Insert in Tx and extract in Rx Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage High throughput for large data transfers on networks supporting jumbo frames Multiple Rx queues Virtualization environment. In this environment, packets dedicated to different virtual machines can be routed to different queues, thus easing the routing of these packets to the target machine. The IO device activates a pre-fetch engine in the CPU that loads the data into the CPU cache ahead of time, before use, eliminating cache misses and reducing CPU load.
Header split replication in receive
Advanced packet filtering
IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags Double Vlan Descriptor ring management hardware for transmit and receive 9.5 kByte jumbo frame support Receive Side Scaling (RSS)
* * *
* * *
VMDq
*
Direct Cache Access (DCA) Fragmented UDP checksum offload for packet reassembly
*
2.5
Manageability Features
Features
Benefits
Advance Pass Through-compatible management packet Tx/Rx support ASF 1.0 and Alert on LAN 2.0 Both ports support Wake on LAN (WoL) SMBus port NC-SI high-bandwidth interface Network management flexibility Manageability DMTF preOS sideband protocol support Promotes customized designs On-board microcontroller Preboot eXecution Environment (PXE) Flash interface support (32-bit and 64-bit) iSCSI Boot Allows packets routing to and from either LAN port and a server management processor Local Flash interface for PXE image Network Management Feature
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82575 Gigabit Ethernet Controller Datasheet
Features
Benefits
Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant including:
* * D0 and D3 power states Network Device Class Power Management Specification 1.1
PCI power management capability requirements for PC and embedded applications Easy system monitoring with industry standard consoles Remote network management capabilities through DMI 2.0 and SNMP software Used to give an indication to the manageability firmware or external devices that the 82575 or the driver is not functioning. Ease of embedded designs
SNMP and RMON statistic counters SDG 3.0, WfM 3.0, and PC2001 compliance Watchdog Timer SGMII interface for embedded applications with an I2C or MDC/MDIO control interface.
2.6
Additional Device Features
Features * * * * * *
Benefits Inherent dual port teaming ability High availability using one port for failover Higher throughput than single Gigabit Ethernet port Lower latency due to one electrical load on the bus Saves critical board space Reduced multi-port Gigabit Ethernet costs Supports backplane and fiber applications as well as copper-based Gigabit via the SGMII interface Link and activity indications (10, 100, and 1000 Mbps) on each port Software definable function (speed, link, and activity) and blinking allowing flexible LED implementations Lower component count and system cost Simplified testing using boundary scan Supports the IDCODE instruction Additional flexibility for LEDs or other low speed I/O devices Validates silicon integrity Standard
Two complete Gigabit Ethernet connections in a single device
Integrated SERDES Four activity and link indication outputs (per port) that directly drive LEDs Programmable LED functionality Internal PLL for clock generation can use a 25 MHz crystal JTAG (IEEE 1149.1) Test Access Port built in silicon Four software definable pins per port Provides loopback capabilities Four-wire SPI EEPROM interface
* * *
* * * * * *
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82575 Gigabit Ethernet Controller Datasheet
2.7
Technology Features
Features
Benefits * 25 mm X 25 mm
576-pin Flip-Chip Ball Grid Array (FC-BGA) package Operating temperature: 1000BASE-T, 0 C to 55 C* 1000BASE-SX/LX (or SERDES backplane), 0 C to 70 C Storage temperature 65 C to 140 C Typical targeted power dissipation: 2.43 W @ D0 1000 Mbps 0.79 W @ D3cold 100 Mbps (wakeup enabled) 0.29 W @ D3cold (wakeup disabled) Maxmum Payload Size: 128 and 256 Max number of transactions (TLP) supported on PCIe: Four TX DMA requests + 1 TX descriptor + 1 RX descriptor
*
Simple thermal design
* *
Conditions: FF materials, nominal voltage, 115 C Minimizes impact of incorporating Gigabit instead of Fast Ethernet.
* *
* For information about operating the 82575 outside of this range, please refer to the 82575 Thermal Management Application Note.
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82575 Gigabit Ethernet Controller Datasheet
3.0
Signal Descriptions and Pinout List
The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82575 controller are electrically defined as follows:
Name
Definition
DC specification See Table 9 See Table 9
I O
Input Standard input only digital signal. Output Standard output only digital signal. Tri-state Bi-directional three-state digital input/ output signal. Open Drain Wired-OR with other agents. The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the deasserted state. Analog PCI Express*, SERDES, or PHY analog signal. Power Power connection, voltage reference, or other reference connection.
TS
See Table 9
OD
See Table 10
A
See Table 10
P
See Table 10
3.2
PCI Express Interface
Symbol
Type
Name and Function
PER_0_N PER_0_P PER_1_N PER_1_P PER_2_N PER_2_P PER_3_N PER_3_P A(I) High Speed Serial Receive Data These signals connect to corresponding PETn and PETp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the transmitter end. The PCI Express differential inputs are clocked at 2.5 Gb/s.
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82575 Gigabit Ethernet Controller Datasheet
Symbol
Type
Name and Function
PET_0_N PET_0_P PET_1_N PET_1_P PET_2_N PET_2_P PET_3_N PET_3_P High Speed Serial Impedance Compensation PE_RCOMP A Connect the recommended resistor value 1.4K from this ball to ground. 100 MHz Differential Clock for the PCI Express Interface A The reference clock is furnished by the system and has a 300 ppm frequency tolerance. PCI Express Reset PE_RST_N I When the signal is low, all PCI Express functions are held in reset. When the signal is high, it denotes that main power is available to the 82575 controller and the reference clock is running. In systems with a PCI Express add-in card, this signal routes to the connector. Wake PE_WAKE_N OD The device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. A(0) High Speed Serial Transmit Data These signals connect to corresponding PERn and PERp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the 82575 controller end. The PCI Express differential outputs are clocked at 2.5 Gb/s.
PE_CLK_P PE_CLK_N
3.3
Power Management Signals
Symbol
Type
Name and Function
Auxiliary Power Present. AUX_PWR I If the Auxiliary Power signal is high, then auxiliary power is present and the 82575device should support the D3cold power state. LAN Disables 0 and 1 LAN0_DIS_N LAN1_DIS_N I Disables individual Ethernet ports. State is latched upon a rising edge of PERST_N or a PCI Express reset event. This pin has an internal pull-up resistor. Device Off Asynchronously disables Ethernet controller. Main Power OK Indicates that platform main power is up. Must be connected externally.
DEV_OFF_N
I
MAIN_PWR_OK
I
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82575 Gigabit Ethernet Controller Datasheet
3.4
System Management Interface Signals
Symbol
Type
Name and Function
SMB Clock SMBCLK OD The SMB Clock signal is an open drain signals for the serial SMB interface. SMB Data SMBD OD The SMB Data signal is an open drain signal for the serial SMB interface. SMB Alert SMBALRT_N OD The SMB Alert signal is an open drain signal for serial SMB Port A. In ASF mode, this signal acts as a power good input. It acts as an alert input in 82559 compatible mode. NCSI Reference Clock Input. Synchronous clock reference for receive, transmit and control interface. It is a 50MHz clock /- 50 ppm. NCSI Reference Clock Output. Synchronous clock reference for receive, transmit and control interface. It is a 50MHz clock /- 50 ppm. Serves as a clock source to the BMC and Zoar (when configured so). Carrier Sense / Receive Data Valid Receive Data. Data signals from the device to the BMC Transmit Enable Transmit Data. Data signals from BMC to the device
NCSI_CLK_IN
I
NCSI_CLK_OUT NCSI_CRS_DV NCSI_RXD[1] NCSI_RXD[0] NCSI_TX_EN NCSI_TXD[1] NCSI_TXD[0]
O O O I I
3.5
MDIO Signals
Symbol
Type
Name and Function
MDC
I
Management Data Clock. Used by the PHY as a clock timing reference for information transfer on the MDIO signal. The MDC is not required to be a continuous signal and can be frozen when no management data is transferred. The MDC signal has a maximum operating frequency of 2.5MHz. Management Data I/O. This internal signaling between the MAC and PHY logically represents a bi-directional data signal used to transfer control information and status to and from the PHY (to read and write the PHY management registers ). Asserting and interpreting value(s) on this interface requires knowledge of the special MDIO protocol to avoid possible internal signal contention or miscommunication to/from the PHY
MDIO
I/O
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82575 Gigabit Ethernet Controller Datasheet
3.6
SPI EEPROM and FLASH Signals
Symbol
Type
Name and Function
EEPROM Data Input EE_DI TS The EEPROM Data Input pin is used for output to the SPI EEPROM memory device. EEPROM Data Output EE_DO I The EEPROM Data Output pin is used for input from the SPI EEPROM memory device. The EE_DO includes an internal pull-up resistor. EEPROM Chip Select The EEPROM Chip Select signal is used to enable the device. EEPROM Serial Clock EE_SK TS The EEPROM Shift Clock provides the clock rate for the SPI EEPROM interface, which is approximately 2 MHz. FLASH Chip Enable Output. Used to enable FLASH device. FLASH Serial Clock Output. FLASH Serial Data Input. This pin is an output to the memory device. FLASH Serial Data Output This pin is an input from the memory device.
EE_CS_N
TS
FLSH_CE_N FLSH_SCK FLSH_SI FLSH_SO
TS TS TS I
3.7
Note:
LED Signals
The LED signals are push-pull (active-high) outputs. They are fully programmable through the EEPROM interface
Symbol
Type
Name and Function
LED0_0 LED0_1
O O
LED0_0. Programmable LED output for Port A. As the Link LED, it indicates link connectivity on Port A. LED0_1. Programmable LED output for Port A. As the Activity LED, it flashes to indicate receive activity on Port A for packets destined for this node. LED0_2 Programmable LED output for Port A. As the Link 100 LED, it indicates link at 100 Mbps for Port A. LED0_3 Programmable LED output for Port A. As the Link 1000 LED, it indicates link at 1000 Mbps for Port A. LED1_0. Programmable LED output for Port B. As the Link LED, it indicates link connectivity on Port B.
LED0_2
O
LED0_3
O
LED1_0
O
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82575 Gigabit Ethernet Controller Datasheet
Symbol
Type
Name and Function
LED1_1 LED1_1 O Programmable LED output for Port B. As the Activity LED, it flashes to indicate receive activity on Port B for packets destined for this node. LED1_2 LED1_2 O Programmable LED output for Port B. As the Link 100 LED, it indicates link at 100 Mbps for Port B. LED1_3 LED1_3 O Programmable LED output for Port B. As the Link 1000 LED, it indicates link at 1000 Mbps for Port B.
3.8
Other Signals
Symbol
Type
Name and Function
SDP0_0 SDP0_1 SDP0_2 SDP0_3 SDP1_0 SDP1_1 SDP1_2 SDP1_3 TS Software Defined Pin (SDP) The Software Defined Pins are programmable with respect to input and output capability. These pins also can optionally be configured as interrupt inputs. SDP signals default to inputs upon power-up, but can be configured differently by the EEPROM.
3.9
Crystal Signals
Symbol
Type
Name and Function
Crystal One XTAL1 AI The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm or better. The other end of the crystal should be connected to XTAL2. Crystal Two XTAL2 AO Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
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82575 Gigabit Ethernet Controller Datasheet
3.10
PHY Analog Signals
Symbol
Type
Name and Function
Compensation Reference Resistor. RBIAS0_P/RBIAS1_P A A 1.4 K, 1% tolerance resistor should be used. RBIAS_N should also be connected to ground (VSS). Media Dependent Interface [0] 1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X configuration, MDIp0/MDIn0 corresponds to BI_DB+/-. 100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. 10BASE-T: In MDI configuration, MDIAp0/MDI_MINUS0_0 is used for the transmit pair, and in MDI-X configuration, MDIp0/ MDIn0 is used for the receive pair. Media Dependent Interface [1] 1000BASE-T: In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in MDI-X configuration, MDIp1/ MDIn1 corresponds to BI_DA+/-. 100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transit pair. 10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transit pair. Media Dependent Interface [2] MDI0_P_2 MDI0_N_2 MDI1_P_2 MDI1_N_2 A 1000BASE-T: In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in MDI-X configuration, MDIp2/ MDIn2 corresponds to BI_DD+/-. 100BASE-TX: Unused. 10BASE-T: Unused. Media Dependent Interface [3] MDI0_P_3 MDI0_N_3 MDI1_P_3 MDI1_N_3 A 1000BASE-T: In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in MDI-X configuration, MDIp3/ MDIn3 corresponds to BI_DC+/-. 100BASE-TX: Unused. 10BASE-T: Unused.
MDI0_P_0 MDI0_N_0 MDI1_P_0 MDI1_N_0 A
MDI0_P_1 MDI0_N_1 MDI1_P_1 MDI1_N_1 A
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82575 Gigabit Ethernet Controller Datasheet
3.11
Serializer/Deserializer Signals
Symbol
Type
Name and Function
SRDSI_0_P SRDSI_0_N SRDSI_1_P SRDSI_1_N SRDSO_0_P SRDSO_0_N SRDSO_1_P SRDSO_1_N AO AI
SERDES Receive Pairs A and B These signals make the differential receive pair for the 1.25 GHz serial interface. For serializer/deserializer operation, the inputs should be coupled to ECL voltage levels. If the SERDES interface is not used, these pins should not be connected. SERDES Transmit Pairs A and B These signals make the differential transmit pair for the 1.25 GHz serial interface. For serializer/deserializer operation, the outputs drive the LVPECL voltage levels. If the SERDES interface is not used, these pins should not be connected. Signal Detects A and B These pins indicate whether the SERDES signals (connected to the 1.25 GHz serial interface) have been detected by the optical transceivers. If the SERDES interface is not used with copper media, these can be left with no connection (NC). If the SERDES interface is not used with fiber media, the SIG_DET inputs should be tied high to VCC. SERDES Impedance Compensation. Connect the recommended resistor (1.4K ) from this ball to ground. Port 0 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin. Port 0 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin Port 1 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin. Port 1 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin
SRDS0_SIG_DET/ SRDS1_SIG_DET
I
SER_RCOMP SFP0_I2C_CLK SFP0_I2C_DATA SFP1_I2C_CLK SFP1_I2C_DATA
A O TS/ OD O TS/ OD
3.12
Note:
Test Interface Signals
Pull-up resistors are needed on these signals as shown in the reference schematic.
Symbol
Type
Name and Function
JTCK JTDI JTDO JTMS
I I OD I
JTAG Test Access Port Clock JTAG Test Access Port Test Data In JTAG Test Access Port Test Data Out JTAG Test Access Port Mode Select
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82575 Gigabit Ethernet Controller Datasheet
3.13
3.13.1
Power Supply Connections
Digital and Analog Supplies
Symbol
Type
Name and Function
VCC3P3
P
3.3 V Digital Power Supply. For I/O circuits. 1.8 V Analog Power Supply For PHY analog, PHY I/O, PCI Express analog, and Phase Lock Loop circuits, Connect all 1.8 V pins to a single power supply. 1.0 V Digital Power Supply For core digital, PHY digital, PCI Express digital and clock circuits, connect all 1.0 V pins to a single power supply.
VCC1P8
P
VCC1P0
P
3.13.2
Grounds, Reserved Pins and No Connects
Symbol
Type
Name and Function
VSS
P
Ground. Reserved, VCC These pins are reserved by Intel and may have factory test functions. For normal operation, connect them directly to VCC. Do not connect them to pull-up resistors. Reserved, Ground These pins are reserved by Intel and may have factory test functions. For normal operation, connect them directly to ground. Do not connect them to pull-down resistors. Reserved, No Connect These pins are reserved by Intel and may have factory test functions. For normal operation, do not connect any circuitry to these pins. Do not connect pull-up or pull-down resistors. No Connect This pin is not connected internally.
RSVD_VCC
RSVD_GND
P
RSVD_ NC
P
NC
P
4.0
Table 1.
Pinout/Signal Name
Pinout
Name
Pin
PE_CLK_P PE_CLK_N
N2 N1
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82575 Gigabit Ethernet Controller Datasheet
PET_0_P PET_0_N PET_1_P PET_1_N PET_2_P PET_2_N PET_3_P PET_3_N
D2 D1 H2 H1 R2 R1 W2 W1
PER_0_P PER_0_N PER_1_P PER_1_N PER_2_P PER_2_N PER_3_P PER_3_N
F2 F1 K2 K1 U2 U1 AA2 AA1
PE_WAKE_N
AC20
PE_RST_N
AC9
PE_RCOMP
L1
RSVDM3_NC RSVDM2_NC
M3 M2
FLSH_SI FLSH_SO FLSH_SCK FLSH_CE_N
AC14 AD14 AD15 AC15
18
82575 Gigabit Ethernet Controller Datasheet
EE_DI EE_DO EE_SK EE_CS_N
A21 A20 B20 B21
SMBD SMBCLK SMBALRT_N
AD21 AC21 AD20
RSVDAD17_NC RSVDAC17_NC RSVDAC16_NC RSVDAD16_NC
AD17 AC17 AC16 AD16
NCSI_CLK_IN NCSI_CLK_OUT
B5 B4
NCSI_CRS_DV NCSI_RXD_1 NCSI_RXD_0
A4 A6 B7
NCSI_TX_EN NCSI_TXD_1 NCSI_TXD_0
B6 A7 B8
SDP0_0 SDP0_1 SDP0_2
A16 B16 B17
19
82575 Gigabit Ethernet Controller Datasheet
SDP0_3
B15
SDP1_0 SDP1_1 SDP1_2 SDP1_3
AD10 A12 A13 AC10
RSVDAB19_NC RSVDAB18_NC
AB19 AB18
RSVDAD9_3P3
AD9
MAIN_PWR_OK
AD4
DEV_OFF_N
B9
RSVDL14_1P0 RSVDP14_1P0
L14 P14
XTAL1 XTAL2
N23 N24
SRDSI_0_P SRDSI_0_N SRDSO_0_P SRDSO_0_N
J23 J24 K23 K24
SRDS0_SIG_DET
A9
SRDSI_1_P SRDSI_1_N SRDSO_1_P SRDSO_1_N
T23 T24 R23 R24
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82575 Gigabit Ethernet Controller Datasheet
SRDS1_SIG_DET
A10
SER_RCOMP
L22
RSVDM23_NC RSVDM24_NC
M23 M24
SFP0_I2C_CLK/ MDC0 SFP0_I2C_DATA/ MDIO0
AD19 AD18
SFP1_I2C_CLK/ MDC1 SFP1_I2C_DATA/ MDIO1
AC19 AC18
LED0_0 LED0_1 LED0_2 LED0_3
A19 B19 B18 A18
LED1_0 LED1_1 LED1_2 LED1_3
AD13 AC11 AC13 AC12
MDI0_P_0 MDI0_N_0 MDI0_P_1 MDI0_N_1 MDI0_P_2 MDI0_N_2 MDI0_P_3
C24 C23 D24 D23 F24 F23 G24
21
82575 Gigabit Ethernet Controller Datasheet
MDI0_N_3
G23
RBIAS0_P VSS
E22 F22
IEEE_TEST0_P IEEE_TEST0_N
A22 B22
MDI1_P_0 MDI1_N_0 MDI1_P_1 MDI1_N_1 MDI1_P_2 MDI1_N_2 MDI1_P_3 MDI1_N_3
AB24 AB23 AA24 AA23 W24 W23 V24 V23
RBIAS1_P VSS
Y22 W22
IEEE_TEST1_P IEEE_TEST1_N
AD22 AC22
RSVDAD8_VSS
AD8
JTCK JTDI JTDO JTMS RSVDAC5_NC
AC6 AD7 AC8 AC7 AC5
AUX_PWR LAN1_DIS_N
B14 A15
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82575 Gigabit Ethernet Controller Datasheet
RSVDB12_NC LAN0_DIS_N RSVDA8_3P3 RSVDA11_3P3 RSVDB10_3P3 RSVDB11_3P3 RSVDA14_VSS
B12 B13 A8 A11 B10 B11 A14
NCB3 NCAC3 NCAD3
B3 AC3 AD3
VCC3P3 VCC3P3 VCC3P3 VCC3P3
AD6 AD12 A5 A17
VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8
P5 P4 N9 N8 N5 N4 M9 M8 M5 M4 L9 L8 L5 L4 L15 K15
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82575 Gigabit Ethernet Controller Datasheet
VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8
J15 H15 G15 E20 E19 D20 D19 Y20 Y19 V15 U15 T15 R15 P15 AA20 AA19 N21 N15 M21 M15 P9 P8
VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0
R14 R13 R12 R11 P13 P12 L13 L12 K14 K13
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82575 Gigabit Ethernet Controller Datasheet
VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0
K12 K11 V5 V4 U5 U4 P11 N11 M11 L11 H5 H4 G5 G4 J21 J20 J18 J17 L21 L20 L18 L17 K21 K20 K18 K17 T21 T20 T18 T17 P21 P20 P18
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82575 Gigabit Ethernet Controller Datasheet
VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0
P17 R21 R20 R18 R17
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y9 Y8 Y7 Y6 Y15 Y14 Y13 Y12 Y11 Y10 W9 W8 W7 W22 W14 W13 W12 W11 W10 V9 V8 V14 V13 V12 V11 V10 U9
26
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U14 U13 U12 U11 U10 T14 T13 T12 T11 N14 N13 N12 M14 M13 M12 J14 J13 J12 J11 H9 H14 H13 H12 H11 H10 G9 G8 G14 G13 G12 G11 G10 F22
27
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F9 F8 F7 F14 F13 F12 F11 F10 E9 E8 E7 E6 E15 E14 E13 E12 E11 E10 D9 D8 D7 D6 D5 D16 D15 D14 D13 D12 D11 D10 C9 C8 C7
28
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C6 C5 C4 C17 C16 C15 C14 C13 C12 C11 C10 B2 B1 AD5 AD2 AD11 AD1 AC4 AC2 AC1 AB9 AB8 AB7 AB6 AB5 AB4 AB17 AB16 AB15 AB14 AB13 AB12 AB11
29
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB10 AA9 AA8 AA7 AA6 AA5 AA16 AA15 AA14 AA13 AA12 AA11 AA10 A3 A2 A1 Y24 Y23 Y21 Y18 Y17 Y16 W21 W20 W19 W18 W17 W16 W15 V22 V21 V20 V19
30
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
V18 V17 V16 U24 U23 U22 U21 U20 U19 U18 U17 U16 T22 T19 T16 R22 R19 R16 P24 P23 P22 P19 P16 N22 N20 N19 N18 N17 N16 M22 M20 M19 M18
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82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M17 M16 L24 L23 L19 L16 K22 K19 K16 J22 J19 J16 H24 H23 H22 H21 H20 H19 H18 H17 H16 G22 G21 G20 G19 G18 G17 G16 F21 F20 F19 F18 F17
32
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F16 F15 E24 E23 E21 E18 E17 E16 D22 D21 D18 D17 C22 C21 C20 C19 C18 B24 B23 AD24 AD23 AC24 AC23 AB22 AB21 AB20 AA22 AA21 AA18 AA17 A24 A23 Y5
33
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y4 Y3 Y2 Y1 W6 W5 W4 W3 V7 V6 V3 V2 V1 U8 U7 U6 U3 T9 T8 T7 T6 T5 T4 T3 T2 T10 T1 R9 R8 R7 R6 R5 R4
34
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
R3 R10 P7 P6 P3 P2 P10 P1 N7 N6 N3 N10 M7 M6 M10 M1 L7 L6 L3 L2 L10 K9 K8 K7 K6 K5 K4 K3 K10 J9 J8 J7 J6
35
82575 Gigabit Ethernet Controller Datasheet
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
J5 J4 J3 J2 J10 J1 H8 H7 H6 H3 G7 G6 G3 G2 G1 F6 F5 F4 F3 E5 E4 E3 E2 E1 D4 D3 C3 C2 C1 AB3 AB2 AB1 AA4
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82575 Gigabit Ethernet Controller Datasheet
VSS
AA3
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82575 Gigabit Ethernet Controller Datasheet
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82575 Gigabit Ethernet Controller Datasheet
5.0
5.1
Table 2.
Power Requirements
Targeted Absolute Maximum Ratings
Absolute Maximum Ratings1
Symbol Parameter Min Max Unit
VCC(3.3) VCC(1.8) VCC(1.0)
DC supply voltage on 3.3 V pins with respect to VSS DC supply voltage on 1.8 V pins with respect to VSS2 DC supply voltage on 1.0 V pins with respect to VSSb 3.3 V I/O Voltage 1.8 V I/O Voltage 1.0 V I/O Voltage DC output current Storage temperature range Case temperature under bias ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/ Undershoot: 150 mA, 125 C
VSS - 0.5 VSS - 0.3 VSS - 0.2 VSS - 0.5 VSS - 0.3 VSS - 0.2 N/A -65 0 N/A
4.6 2.5 1.7 4.6 2.5 1.7 TBD 140 85 VDD overstress: VDD(3.3) * (7.2 V)
V V V
VI / V O IO Tstorage Tcase
V mA C C V
1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal device operations. 2. During normal device power up and power down, the 1.8 V and 1.0 V supplies must not ramp before the 3.3 V supply.
5.2
5.2.1
Table 3.
Targeted Recommended Operating Conditions
General Operating Conditions
Recommended Operating Conditions 1
Symbol Parameter Min Max Unit
VCC(3.3) VCC(1.8) VCC(1.0) tR / tF Ta TJ
DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.0 V pins Input rise/fall time (normal input) Operating temperature range (ambient) Junction temperature
3.0 1.71 0.95 0 0 N/A
3.6 1.89 1.05 200 55 110
V V V ns C C
1. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. Device functionality to stated DC and AC limits is not guaranteed, if conditions exceed recommended operating conditions.
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82575 Gigabit Ethernet Controller Datasheet
5.2.2
Table 4.
Voltage Ramp and Sequencing Recommendations
The following tables give the specifications for the power supply ramps: 3.3 V Supply Voltage Ramp
Parameter Description Min Max Unit
Rise Time Monotonicity Slope Operational Range Ripple Ripple Overshoot
Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 50 MHz Overshoot time upon ramp2 Maximum voltage allowed
b
0.1 N/A 24 3 N/A N/A N/A
1001 0 28800 3.6 70 0.05 100
ms mV mV/ms V mVpeak-peak ms mV
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability.
Table 5.
1.8 V Supply Voltage Ramp
Parameter Description Min Max Unit
Rise Time Monotonicity Slope Operational Range Ripple Overshoot SettlingTime Overshoot
Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 1 MHz Overshoot time upon ramp2 Maximum voltage allowedb
0.1 N/A 14 1.71 N/A N/A N/A
1001 0 60000 1.89 40 0.1 100
ms mV mV/ms V mVpeak-peak ms mV
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability.
Table 6.
1.0 V Supply Voltage Ramp
Parameter Description Min Max Unit
Rise Time Monotonicity Slope Operational Range
Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions
0.1 N/A 7.6 0.95
1001 0 33600 1.05
ms mV mV/ms V
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82575 Gigabit Ethernet Controller Datasheet
Ripple Overshoot SettlingTime Overshoot
Maximum voltage ripple at a bandwidth equal to 1 MHz Overshoot time upon ramp2 Maximum voltage allowedb
N/A N/A N/A
40 0.05 100
mVpeak-peak ms mV
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. 2. Excessive overshoot can affect long term reliability.
Table 7.
Power Supply Sequencing
Symbol Parameter Min Max Unit
T3 18 T18 1 T3 1 Tm-per, Tm-ppo Tper-m, Tppo-m
VCC3p3 (3.3 V) stable to VCC1p8 stable VCC1p8 stable to VCC (1.0 V) stable VCC3p3 (3.3 V) stable to VCC (1.0 V) stable 3.3 V core to GIO_PWR_GOOD and MAIN_PWR_OK on GIO_PWR_GOOD, MAIN_PWR_OK off before 3.3 V core down
0 0 0 TBD 0
100
ms ms
100
mV ms ms
Aux power stable
VCCP (3.3V) VCC1p8 (1.8V) VCC/VCC1p0(1V) Power-on Reset (internal)
T3_18 T18_1 Tlpgw
T3_1 Tlpg Main Power stable
Main power stable GIO_PWR_GOOD MAIN_PWR_OK
Tm-per Tm-ppo Tlpg-per Tper-m Tppo-m
Figure 2.
Voltage Power Sequencing Options To meet the 375 mA inrush current requirements (not including external capacitors) the ramp time should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5 ms), expect higher inrush current due to the high charging current of the decoupling capacitors of 3.3 V, 1.8 V and 1.0 V rails.
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82575 Gigabit Ethernet Controller Datasheet
6.0
Thermal
The 82575 device is specified for operation when the ambient temperature (TA) is within the range of 0 C to 55 C. For information about the thermal characteristics of the device, including operation outside this range, please refer to the 82575 Thermal Application Note.
7.0
7.1
Table 8.
Electrical Specification
DC Specifications
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
VCC(3.3) VCC(1.8) VCC(1.0)
DC supply voltage on 3.3 V pins DC supply voltage on 1.8 V pins DC supply voltage on 1.0 V pins
3.00 1.71 0.95
3.30 1.80 1.00
3.60 1.89 1.05
V V V
Table 9.
I/O Characteristics
Symbol
Parameter
Condition1
Min
Typ
Max
Units
VIH VIL IIN
Input high voltage Input low voltage Input current VIN = VDD(3.3) or VSS IOH = -16 mA VCC = Min IOH = -100 A VCC = Min IOL = 14 mA VCC = Min IOL = 100 A VCC = Min
2.0 -0.5 -15 2.4 VCC - 0.02 N/A N/A -10 N/A 2.6 N/A N/A
N/A N/A N/A N/A N/A N/A N/A N/A 2.5 N/A N/A N/A
VCC(3.3) + 0.5 0.8 15 N/A
V V A
VOH
Output high voltage
V N/A 0.4 V 0.2 10 N/A 5.5 4.0 -0.4 A pF k V V
VOL
Output low voltage
IOZ CIN2 PU VOS VUS
Off-state output leakage current Input capacitance Internal pull-up Overshoot Undershoot
VO = VCC or VSS
1. The input buffer also has hysteresis > 160 mV.
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82575 Gigabit Ethernet Controller Datasheet
2. Cin= 2.5 pF(maximum input capacitance), Cout = 16 pF (characterized max output load capacitance per 160 MHz).
Table 10.
Open Drain I/O
Symbol
Parameter
Condition
Min
Max
Units
Note
VCC3P3 VCC Vih Vil Ileakage Vol Ipullup Cin Cout Ioffsmb
Periphery supply Core supply Input High Voltage Input Low Voltage Output Leakage Current Output Low Voltage Current sinking Input Pin Capacitance Output Pin Capacitance Input leakage current
Notes: 1. 2. 3. 4.
3.0 0.9 2.1
3.6 1.32
V V V
0.8 0 < Vin < VCC3P3 @ Ipullup Vol=0.4V 4 7 30 VCC3P3 off or floating +/-10 +/-10 0.4
V iA V mA pF pF iA 3 3 2 2 4
Applies to SMBD0, SMBCLK0, , SMBALRT _N, PE_WAKE_n, SFP1_I2C_Data, SFP0_I2C_Data pads. Device meets this whether powered or not. Characterized, not tested. OD no high output drive. VOL max=0.4V at 14mA, VOL max=0.2V at 0.1mA
Table 11.
Power Consumption
D0a--Active Link @10 Mbps Typ Icc (mA)1 3.3 V 1.8 V 1.0 V Total Device Power @100 Mbps Typ Icc (mA)1 @ 1000 Mbps (copper) Typ Icc (mA)1 Max Icc (mA)1 @ 1000 Mbps (SERDES) Typ Icc (mA)1 Max Icc (mA)2
18 344 304 0.98 W
18 312 388 1.01 W
18 841 856 2.43 W
23 856 1184 2.80 W
19 142 354 0.67 W
19 203 492 0.92 W
1. Typical conditions: operating temperature (TA) = 25 C, nominal voltages and moderate network traffic at full duplex. 2. Maximum conditions: maximum operating temperature (TJ) values, typical voltage values and continuous network traffic at full duplex.
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82575 Gigabit Ethernet Controller Datasheet
D0a--Idle Link Unplugged--no link LOs only Typ Icc (mA)1 3.3 V 1.8 V 1.0 V Total Device Power2
18 129 264 0.56
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 2. Known errata on LOs & L1 states might impact devide power consumption
D0a--Idle Link @10Mbps LOs only Typ Icc (mA)1 3.3 V 1.8 V 1.0 V Total Device Power2
18 140 302 0.61 W
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 2. Known errata on LOs & L1 states might impact devide power consumption
D0a--Idle Link @100Mbps (Copper) LOs only Typ Icc (mA)1 3.3 V
18
45
82575 Gigabit Ethernet Controller Datasheet
D0a--Idle Link @100Mbps (Copper) LOs only Typ Icc (mA)1 1.8 V 1.0 V Total Device Power2
837 755 2.32 W
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 2. Known errata on LOs & L1 states might impact devide power consumption
D0a--Idle Link @1000Mbps (SERDES) Typ Icc (mA)1 3.3 V 1.8 V 1.0 V Total Device Power2
17 142 341 0.65 W
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 2. Known errata on LOs & L1 states might impact devide power consumption
D3cold - wake-up enabled @10 Mbps @100 Mbps
D3coldwake disabled
Typ Icc (mA)
3.3 V
Typ Icc (mA) 18
Typ Icc (mA) 18
18
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82575 Gigabit Ethernet Controller Datasheet
D3cold - wake-up enabled @10 Mbps @100 Mbps
D3coldwake disabled
Typ Icc (mA)
1.8 V 1.0 V Total Device Power
Typ Icc (mA) 269 249 0.79 W
Typ Icc (mA) 83 70 0.29 W
98 168 0.40 W
D(r) Uninitialized Disabled through DEV_OFF_N Typ Icc (mA) 3.3 V 1.8 V 1.0 V Total Device Power
11 179 283 0.64
7.2
Resets
Power-on Reset (internal): The 82575 has an internal mechanism for sensing the power pins. Once the power is up and stable, it creates an internal reset, this reset acts as a master reset of the entire chip. It is level sensitive, and while it is 0, will hold all of the registers in reset. Power-on Reset is interpreted to be an indication that device power supplies are all stable. Power-on Reset changes state during system power-up. In-band PCIe Reset: The 82575 will generate an internal reset in response to a physical layer message from the PCIe or when the PCIe link halts (entry to Polling or Detect state). This reset is equivalent to PCI reset in previous (PCI) gigabit LAN controllers. Main_Power_Good: Used by the device to detect the D3Cold condition and activate part of the power saving scheme. Also used to change the state of the ASF manageability firmware.
47
82575 Gigabit Ethernet Controller Datasheet
7.3
Table 12.
Pull-up and Pull-down Specifications and Signals
Internal and External Pull-up and Pull-down Values
Min PU (Internal) PU (External, recommende d) PD (External, reccommend ed) 2.7K
Nominal 5K
Max 8.6K
Units
<3K
<400
For external Pull-up requirements, see the 82575 reference schematics. The table below lists internal & external pull-up resistors and whether they are activated in the different device states. Each internal PUP has a nominal value of 5k, ranging from 2.7K to 8.6K. The device states are defined as follow: Power-up = while 3.3 V is stable, but not 1.0 V Active = normal mode (not power up nor disable) Disable = device disabled Table 13. Internal Pull-up and External Pull Up Requirements
Signal Name
Power up
Active
Disable
External Recomended?
Notes
PE_WAKE_N PE_RST_N FLSH_SI FLSH_SO FLSH_SCK FLSH_CE_N EE_DI EE_DO EE_SK EE_CS_N SMBD SMBCLK SMBALRT_N
N Y Y Y Y Y Y Y Y Y N N N
N N N Y N N N Y N N N N N
N N Y Y Y Y Y Y Y Y N N N
Y N N N N Y N N N Y Y Y Y
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82575 Gigabit Ethernet Controller Datasheet
NCSI_CLK_IN NCSI_CLK_OUT NCSI_CRS_DV
N Y N
N N N
N N N
N N Y Pull down only if NCSI is NOT being used or configured for multi drop Pull Up only if NCSI is NOT being used or configured for multi drop Should be connected to external PD if NCSI is NOT used Should be connected to external PD if NCSI is NOT used
NCSI_RXD[1:0]
N
N
N
Y
NCSI_TX_EN
N
N
N
N
NCSI_TXD[1:0] SDP0[3:0] SDP1[3:0] DEV_OFF_N
N Y Y Y
N Y Y N
N N N N
N N N Must be connected on board Must be connected on board Must be connected externally Must be connected externally Y if active Y Y if active Y
MAIN_PWR_OK
Y
N
N
SRDS_0_SIG_DET
Y
N
N
SRDS_1_SIG_DET SFP0_I2C_CLK SFP0_I2C_DATA SFP1_I2C_CLK SFP1_I2C_DATA LED0_0 LED0_1 LED0_2 LED0_3 LED1_0 LED1_1 LED1_2 LED1_3 JTCK
Y Y Y Y Y Y Y Y Y Y Y Y Y Y
N N N N N N N N N N N N N N
N Y N Y N N N N N N N N N N
If used. If used. If used. If used.
N
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82575 Gigabit Ethernet Controller Datasheet
JTDI JTDO JTMS AUX_PWR LAN1_DIS_N LAN0_DIS_N
Y Y Y Y Y Y
N N N N Y Y
N N N N Y Y
Y Y Y Y (or PD)
7.4
Table 14.
Targeted AC Characteristics
25 MHz Clock Input Requirements
Symbol Parameter Frequency Frequency Variation Duty Cycle Rise Time Fall Time Clock Jitter (peak-to-peak)1 Input Capacitance Operating Temperature Input clock amplitude (peak-topeak) Clock common mode Min Typ Max Unit
f0 df0 Dc tr tf Jptp Cin T Aptp Vcm
N/A -50 40 N/A N/A N/A N/A N/A 1.0 N/A
25.000 N/A N/A N/A N/A N/A 20 N/A 1.2 0.6
N/A +50 60 5 5 250 N/A 70 1.3 N/A
MHz ppm % ns ns ps pF C V V
1. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at least 105 clock edges, filtered by HPF with cut off frequency of 5000 Hz).
Table 15.
Link Interface Clock Requirements
Symbol
Parameter
Min
Typ
Max
Unit
fGTX
1
GTX_CLK frequency
N/A
125
N/A
MHz
1. GTX_CLK is used externally for test purposes only. See signals IEEE_TEST1_p and IEEE_TEST1_n.
7.4.1
EEPROM Interface
Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3 V, Cload = 1 TTL Gate and 16pF (unless otherwise noted).
Symbol
Parameter
Min
Typ
Max
Units
Note
50
82575 Gigabit Ethernet Controller Datasheet
tSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tV tHO tDIS
SCK clock frequency Input rise time Input fall time SCK high time SCK low time CS high time CS setup time CS hold time Data-in setup time Data-in hold time Output valid Output hold time Output disable time
0
2 2.5ns 2.5ns
2.1 2 2
MHz us us ns ns ns ns ns ns ns
[1]
200 200 250 250 250 50 50 0 0
250 250
[2]
200
ns ns
250
ns
1. 2.
Clock is 2MHz 50% duty cycle
tCS VIH CS VIL VIH SCK VIL tSU VIH SI VIL tV VIH SO VIL Hi-Z tHO tDIO Hi-Z VALID IN tH tCSS tWL tWH
tCSH
Figure 3.
EEPROM Interface Time Diagram
7.4.2
FLASH Interface
Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3 V, Cload = 1 TTL Gate and 16 pF (unless otherwise noted)
51
82575 Gigabit Ethernet Controller Datasheet
Table 16.
FLASH Parameters
Symbol
Parameter
Min
Typ
Max
Units
Note
tSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tV tHO tDIS
SCK clock frequency Input rise time Input fall time SCK high time SCK low time CS high time CS setup time CS hold time Data-in setup time Data-in hold time Output valid Output hold time Output disable time
0
15.625 2.5 2.5
20 20 20
MHz ns ns ns ns ns ns ns ns ns
[1]
20 20 25 25 25 5 5
32 32
[2] [2]
20 0 100
ns ns ns
tCS VIH CS VIL tcss VIH Sck VIL tSU VIH SI VIL tv SO VOH VOL HI-Z tHO tDIS HI-Z VALID IN tH tWH tWL
tCSH
Figure 4.
FLASH Timing Diagram
7.4.3
Table 17.
NC-SI Interface
NC-SI AC Specification
Symbol
Parameter
Min
Typ
Max
Units
Notes
52
82575 Gigabit Ethernet Controller Datasheet
REF_CLK Frequency REF_CLK Duty Cycle REF_CLK accuracy Tsu Thold Tval Tor Tof Todr1 Todf1 Tidr2 Tidf2 Tir Tif TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge TXD[1:0], TX_EN Data hold from REF_CLK rising edge RXD[1:0], CRS_DV Data valid from REF_CLK rising edge RXD[1:0], CRS_DV Output Time rise RXD[1:0], CRS_DV Output Time fall RXD[1:0], CRS_DV Output delay rise RXD[1:0], CRS_DV Output delay fall TXD[1:0], TX_EN Input delay rise TXD[1:0], TX_EN Input delay fall TXD[1:0], TX_EN Input Time rise TXD[1:0], TX_EN Input Time fall 3 1.5 1.8 0.5 0.5 2 2 0.5 0.5 0.02 0.02 35
50 65 100
MHz % ppm ns ns 9 6 6 5.8 5.8 6 6 0.15 0.15 ns ns ns ns ns ns ns ns ns
2 1
6
3 3 3 3 4, 5 4, 5 4, 5 4, 5
Notes: 1. Clock Duty cycle measurement: High interval measured from Vih to Vil points, Low from Vil to next Vih 2. Clock interval measurement from Vih to Vih 3. Cload = 25 pF 4. Cload = 200 fF 5. The input delay test conditions: Maximum input level = VIN = 2.7V; Input rise/fall time (0.2VIN to 0.8VIN) = 1ns (Slew Rate ~ 1.5ns). 6. The NC-SI specification defines a hold time of 1.0 ns. In order to work with the 82575, the board designer should guarantee a hold time of 1.5 ns.
7.4.4
Table 18.
SMBus Interface
SMBus AC Characteristics (master mode)
Symbol FSMB TBUF THD:STA TSU:STA TSU:STO THD:DAT TTIMEOUT TLOW
Parameter SMBus Frequency Time between STOP and START condition driven by the device Hold time after Start Condition. After this period, the first clock is generated. Start Condition setup time Stop Condition setup time Data hold time Detect SMBClk low timeout SMBClk low time
Min
Typ 74.4 6.56 6.72
Max 100
Units kHz s s s
6.88 0.48 26.2 5.76 31.5
s s ms s
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82575 Gigabit Ethernet Controller Datasheet
THIGH
SMBClk high time
6.56
s
Table 19.
SMBus AC Characteristics (slave mode)
Symbol
Parameter
Min
Typ
Max
Units
FSMB TBUF THD:STA TSU:STA TSU:STO THD:DAT TTIMEOUT TLOW THIGH
SMBus Frequency Time between STOP and START condition driven by the device Hold time after Start Condition. After this period, the first clock is generated. Start Condition setup time Stop Condition setup time Data hold time Detect SMBClk low timeout SMBClk low time SMBClk high time 26.2
74.4 6.56 6.72 TBD 6.88 0.48
100
kHz s s s s s
31.5 5.76 6.56
ms s s
Table 20.
AC Test Loads for General Output Pins
Symbol Parameter Min Typ Max Unit
CL
Capacitance of test load
N/A
16
N/A
pF
CL
Figure 5.
AC Test Loads for General Output Pins
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82575 Gigabit Ethernet Controller Datasheet
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82575 Gigabit Ethernet Controller Datasheet
8.0
Table 21.
Crystal Requirements
Reference Crystal Specification Requirements
Parameter Name
Symbol
Recommended Value
Conditions
Frequency Vibration mode Cut Operating /Calibration Mode Frequency Tolerance @25C Temperature Tolerance Operating Temperature Non Operating Temperature Range Equivalent Series Resistance (ESR) Load Capacitance Shunt Capacitance Pullability from Nominal Load Capacitance Max Drive Level Insulation Resistance Aging Differential board capacitance* Board Capacitance External Capacitors Board Resistance
fo
25.000 [MHz] Fundamental AT Parallel
@25 [C]
f/fo @25C f/fo Topr Topr Rs Cload Co f/Cload DL IR f/fo CD Cs C1, C2 Rs
30 [ppm] 30 [ppm] -20 to +70 [C] -40 to +90 [C] 50 [U] maximum 20 [pF] (max 24pF) 6 [pF] maximum 15 [ppm/pF] maximum 0.5 [mW] 500 [M] minimum 5 [ppm/year[ 2 [pF] 4 [pF] 27 [pF] 0.1 []
@25 [C]
@25 [MHz]
@ 100V DC
9.0
LED Configuration
The 82575provides 4 LEDs per port that may be used to indicate the status of the traffic. The default setup of the LEDs is done via the EEPROM words 1Ch and 1Fh. The default setup for both ports is the same. This setup is reflected in the LEDCTL register of each port. Each driver may change its setup individually. For each of the LEDs the following parameters can be defined: 1. Mode: Defines which information is reflected by this LED. The encoding is described in the LEDCTL register. 2. Polarity: Defines the polarity of the LED. 3. Blink mode: should the LED blink or be stable. In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or 83 ms for each phase. There is one rate for all LEDs
56
82575 Gigabit Ethernet Controller Datasheet
10.0
Mechanical Information
This section describes the 82575 device physical characteristics. The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
10.1
Targeted Package Information
The 82575device is a 576-lead flip-chip ball grid array (FC-BGA) measuring 25 mm by 25 mm. The nominal ball pitch is 1 mm. See Figure 9.
Detail Area
0.43 mm Solder Resist Opening
0.62 mm Metal Diameter
57
82575 Gigabit Ethernet Controller Datasheet
58
82575 Gigabit Ethernet Controller Datasheet
Figure 6.
82575 Mechanical Specifications
59
82575 Gigabit Ethernet Controller Datasheet
10.2
Figure 7.
Visual Pin Assignments
This section contains the illustrations of the pin outs. 82575 Visual Pin Assignment Part 1 (Top View)
VSS
60
82575 Gigabit Ethernet Controller Datasheet
Figure 8.
82575 Visual Pin Assignment Part 2 (Top View)
61
82575 Gigabit Ethernet Controller Datasheet
Figure 9.
82575 Visual Pin Assignment Part 3(Top View)
62
82575 Gigabit Ethernet Controller Datasheet
Figure 10.
82575 Visual Pin Assignment Part 4 (Top View)
63

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